CHIP DESIGNER AMD has been talking up some of the x86 design features for its first Fusion processor at the International Solid State Circuits Conference (ISSCC) in San Francisco this week. The upcoming 'Llano' Accelerated Processing Unit (APU) will see the joining of a 32nm silicon-on-insulator (SoI) Phenom II quad core CPU with a DirectX 11 capable GPU on the same die. This is a more sophisticated approach than Intel's at present, in which it simply adds a GPU chip to the processor package and calls that 'integrated'. According to AMD senior fellow Samuel Naffziger, the company has focused heavily on cutting power usage in the x86 section of the APU, allowing more juice for the GPU and keeping heat generation and power waste to a minimum. The SoI approach enables core level power gating-to-ground, thereby allowing the use of NFET transistors rather than the bulkier and more sluggish PFET transistors for power gating while negating the need for a special thick metal layer on the die to handle gate supply redistribution.
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