AMD 45nm Shanghai to have improved IPC

Instructions per clock
by Fuad Abazovic Thursday, 08 May 2008

AMD's Server VP has officially talked about the new server plans and Randy Allen, Corporate Vice President and General Manager for server and workstation market, has said that the upcoming 45nm Shanghai core is still on track for 2H 2008. We can remind you that Dirk Meyer, the second in charge at AMD, has said that volume production of 45nm quad-cores, including Shanghai, will start in Q4 2008.The new Shanghai design will feature coherent HyperTransport 3.0 for processor to processor communication. The new 45nm Quad-core will also increase the amount of shared L3 cache from 2MB with current Barcelona design to 6MB with Shanghai, and this new Chinese chip promises instruction per clock (IPC) enhancements.

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