Intel-Backed Chip Tech Deliberately Gets It Wrong

By Mark Hachman February 9, 2009

In 1994, a flaw in the lookup table used by Intel's Pentium floating-point unit produced seemingly random errors. Now, fifteen years later, computing errors are being used for a sort of "good-enough computing" that could promise dramatically reduced power consumption. At the International Solid-State Circuits Conference Monday morning on San Francisco, a team of Rice University researchers will unveil a type of chip called "probabilistic CMOS, or PCMOS, which promises to be about seven times faster than conventional CMOS. The team's research was funded by Intel as well as DARPA, the Defense Advanced Research Projects Agency. According to the team, conventional CMOS has been constantly improved by increasing the chip's operating voltage to reduce errors. The tradeoff is increased power. In certain environments, however, probabilistic logic assumes that some errors will be accepted by a user as a tradeoff for dramatically lower power: in mobile video, for example, users might accept some video artifacts caused by errors introduced in the calculation of the algorithm. Another application may be encryption, which embraces random errors to improve the complexity of the encryption algorithm.

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