By Paul Taylor: Wednesday, 18 June 2008
THERE’S A GEEK-FEST TAKING PLACE in Hawai’i, of all places, and it’s called the VLSI Symposia – that’s fine by us, give us a working vacation any day over…uhm… work. The crammed brains-in-attendance have been able to show some interesting developments in the field of semiconductor research – including Intel’s own slideware which they’ve so graciously sent us for analysis. If you’ve been following Intel’s achievements over the past few years, you’ll have noticed that Chipzilla is they are repeatedly reaching the design limit on a few elements in their chips. The latest example had been the leaky 45nm process, which they bathed in Hafnium and gave high-K metal gates. Now Intel is trying to push cache to a guesstimated 3 to 4 times its current capacity by using Floating Body Cells (FBC). Floating Body Cells have nothing to do with corpses bobbing up and down in the Hudson River. It’s all about SOI, and although Intel didn’t like IBM/AMD’s SOI back in the daze they like it enough now that they need it. The FBC (your bit of storage) hangs under the gate and over the 10nm thin buried oxide (BOX) layer, meaning its small, simple (ie: cost effective) and – from what we garner, won’t suffer from the electric shortcomings of current DRAM designs. Intel also says it’s a bit more scalable than previous caches. This would also, potentially, lead to a new species of DRAM some time down the line, but Intel’s business isn’t about building DRAM, it’s about building CPUs.
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